Resolver
Sine cosine to angle
The Resolver IP consists of two separate modules.
In power board FPGA IP, the resolver exciter shall be implemented using desired technology (FPGA assisted, full analog solution, mixed mode).
In motor control FPGA IP the Resolver IP decode SINE/COSINE/EXCITER analog inputs to generate motor electric angle.
A linear interpolation is used to creates intermediates angle when analog signal is not valid for direct evaluation.