Out motor control software is designed to operate on Xilinx FPGA and achieve superb performance from high performance motors.
Control PMSM motors in sensorless mode up to 500 Krpm
The Field Orient Control cycle time is up to 3.2 μs at 50 MHz
and 1.6 μs at 100 MHz.
Multi controls in single FPGA to reduce synchronization time and cost in complex architecture.
Reduced EMI by spreading of modulation frequency and evaluation of DC-LINK at every FOC cycle
The RPFM modulator reduce latency time form math to pysical layer. This reduce effective execution time of whole current control loop.
Multi level implemented with RPFM modulator to increment voltage and angle resolution and reducing ripple current at low modulation index
IP H/W PROTECTION
The Physical layer is protected against overload trough fast analog acquisition system. The over current protection works on motor phases, on motor current vector and on DC-LINK current.
IP LIFE CYCLE
The motor control IP consists of common core and a separate physical layer IP. The high reusability of common core simplify the maintenance of s/w stack. The confinement in a separate IP of the physical layer guarantees flexibility and adaptability to systems from a few watts to big power trains.
All alternative IP's such as modulators and rotor angle position systems can be selected on the fly by s/w controllable multiplexors. All IP's sub modules can be programmed on the fly according working condition.
Zero s/w application using HDL/HLS code trough Vivado/Vivado/HLS®.
The application s/w can be BareMetal to Multi-Thread using Linux/QNX operating systems.
From VDHL and HLS to Microblaze ® and ARM Cortex-R/A. The FPGA solution is the right technology for distributed computation instances for different realtime constraints.