MOTOR CONTROL AGENT – MCA
MOTOR CONTROL AGENT - MCA
The upper layer of Motor Control FPGA IP is AXI4-Lite IP interface for easily interconnect the Microblaze, Zynq and ZynqMP microcontrollers
Moving from h/w domain to s/w domain we have two main option: Bare Metal and Operating System.
The s/w Is fully realized with Xilinx SDK s/w tool in “C” language.
The Board Specific Platform s/w shall include the supplied s/w drivers for Motor Control FPGA IP and Power board FPGA IP
the following list correspond to main implemented functions:
- interface with Motor Control FPGA IP and Power Board FPGA IP s/w drivers for direct access to memory mapped 32-bits h/w registers
- tiny UDP/IP application protocol with minimum usage of memory. This protocol is the server side of MCM client protocol
- light CLI (command line interface) using UART configured with 115200,8,n,1
- usage of single ARM core (Zynq and ZynqMP) or Microblaze
- require h/w timer for timings (AXI timer if Microblaze, and PL timer if Zynq,ZynqMP)
- require Ethernet MAC (AXI EthernetL if Microblaze, and PL MAC if Zynq,ZynqMP)
- interrupt-free. No interrupt is used: the s/w works in polling mode without live loops.
- remote flash Read/Erase/Program of QSPI memory (support single chip interface)
- can be extended to guest embedded application functionalities
- in case of Zynq the code can be executed in single QSPI memory or OCM with or without external DDR memory
This s/w is supplied in open source code and can be used and modified if used with QDESYS IP
LINUX OPERATING SYSTEM
- In Linux operating system the access to FPGA PL and h/w resources require a kernel driver.
The AMD/Xilinx PetaLinux Tools offer a simply procedure to create a FPGA Linux boot file and root file system getting h/w platform information from Petalinux BSP and and FPGA PL project achitecture from Vivado HDF file (handoff file from Vivado to Vitis).
QDESYS supply the following s/w items:
- qmfoc.ko : dynamic loadable kernel module.
- libqmfoc.so : shared library
- qmfocctl : utility program
- feeds internal data structure and get s/w resources from Kernel according Linux device-tree generated by petalinux tools.
- implement UDP/IP server protocol compatible with MCA Bare Metal s/w
- direct access to FPGA PL AXI-bus motor control IP’s trough Linux interface: open(), close(), ioctl()
- background thread function for periodic process such as read temperatures and s/w watch-dog to monitor application healty
- read/write XML file for motor configuration
- math compiler to convert engineering parameter into motor control FPGA IP h/w register
- configuration of qmfoc.ko driver with Vivado HDF file (alternative to device-tree mode)
- export of function compatible with remote MCA GUI DLL functions
- function wrapper for python.
- program qmfoc.ko with Vivado HDF file