Pulse Width Modulator
The PWM modulator runs at FPGA main clock so the fundamental frequency is an integer divide of FPGA clock.
The modulation waveform is based on high resolution LUT (look up table) with linear interpolation to minimize the ripple.
A classic SINE waveform and a SINE waveform plus 3rd order harmonic are default available waveforms.
Assuming the sinusoidal modulator can transfer 100% of DC_LINK to motor, the space vector modulation can transfer more than 115%
The DC_LINK voltage is evaluate at every PWM cycle.
A common mode offset can be optionally added to remove narrow commands to gate unit. The drawback is increasing of switches per seconds.